View ADV7282WBCPZ_7436675.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

10- bit, 4 oversampled sdtv video decoder with differential inputs and deinterlacer data sheet adv7282 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent r ights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features worldwide ntsc/pal/secam color demodulation support one 10 - bit analog - to - digital converter (adc), 4 oversampling per channel for cvbs, y/c, and yprpb modes adv7282 : 4 analog video inp ut channels with on - chip antialiasing filter adv7282 - m : 6 analog video input channels with on - chip antialiasing filter video input support for cvbs (composite), y/c (s - video), and yprpb (compo nent) fully differential, pseudo differential, and single - ended cvbs video input support ntsc/pal/secam autodetection short - to - battery (stb) diagnostics on 2 video inputs up to 4 v common - mode input range solution excellent common - mode noise rejection capa bilities 5 - line adaptive 2d comb filter and cti video enhancement adaptive digital line length tracking (adllt), signal processing, and enhanced fifo management provide mini - time base correction (tbc) functionality integrated automatic gain control (agc) w ith adaptive peak white mode f ast switch ing capability integrated interlaced - to - progressive (i2p) video output converter ( d einterlacer) adaptive contrast enhancement (ace) down dither (8 - bit to 6 - bit) rovi (macrovision) copy protection detection 8 - bit itu - r bt.656 ycrcb 4:2:2 output ( adv7282 ) mipi csi - 2 output interface ( adv7282 - m only) full featured vertical blanking interval (vbi) d ata slicer with world system teletext (wst) support power - down mode available 2 - wire , i 2 c - compatible serial interface qualified for automotive applications ? 40c to +105c temperature grade 32- lead, 5 mm 5 mm, rohs - compliant lfcsp applications smartphon e/multimedia handsets automotive infotainment dvrs for video security media players general description the adv7282 / adv7282 - m are v ersatile one - chip, multiformat video decoder s . the adv7282 / adv7282 - m automatically detects standard analog baseband video signals co mpatible with worldwide ntsc, pal, and secam standards in the form of composite, s - video, and component video. the adv7282 converts the analog video signals into a ycrcb 4:2:2 video data strea m that is compatible with the 8 - bit itu - r bt.656 interface standard. the adv7282 - m converts the analog video signals into an 8 - bit ycrcb 4:2:2 video data stream that is output over a mobile indus try processor interface (mipi?) csi - 2 interface . the analog video inputs of the adv7282 / adv7282 - m accept single - ended, pseudo differ ential, and fully differential signals. the adv7282 / adv7282 - m contain a deinterlacer ( i2p con - verter ) and short to battery detectio n capability with two stb diagnostic pins. the adv7282 provides four analog inputs. the adv7282 - m provides six analog inputs and th ree general - purpose outputs. the adv7282 / adv7282 - m are programmed via a 2 - wire, serial bidirectional port (i 2 c compatible) and is fa bricated in a 1.8 v cmos process. the lfcsp package option makes the decoder ideal for space - constrained portable applications.
adv7282 data sheet rev. a | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagrams ............................................................. 3 specifications ..................................................................................... 4 electrical specifications ............................................................... 4 video specifications ..................................................................... 5 analog specifications ................................................................... 6 clock and i 2 c timing specifications ......................................... 6 mipi video output specifications (adv7282 - m only) ........ 7 pixel port timing specifications (adv7282 only) ................. 9 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 reflow solder .............................................................................. 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 theory of operation ...................................................................... 13 analog front end (afe) ........................................................... 13 standard definition processor (sdp) ...................................... 14 power supply seq uencing .............................................................. 15 optimal power - up sequence .................................................... 15 simplified power - up sequence ................................................ 15 power - down sequence .............................................................. 15 d vddio supply voltage ................................................................ 15 input networks ............................................................................... 16 single - ended input network .................................................... 16 differential input network ....................................................... 16 short - to - battery protection ...................................................... 16 input configuration ....................................................................... 17 short - to - battery (stb) diagnostics ............................................. 18 programming the stb diagnostic function .......................... 18 adaptive contrast enhancement (ace) ..................................... 20 i2p function .................................................................................... 21 itu - r bt.656 tx configuration (adv7282 only) .................. 22 mipi csi - 2 output (adv7282 - m only) ................................... 23 i 2 c port description ....................................................................... 24 register maps .............................................................................. 25 pcb layout recommendations .................................................... 27 analog interface inputs ............................................................. 27 power supply decoupling ......................................................... 27 vrefn and vrefp pins .......................................................... 27 digital outputs ........................................................................... 27 exposed metal pad ..................................................................... 27 digital inputs .............................................................................. 27 mipi outputs (d0p, d0n, clkp, clkn) adv7282 - m o nly .............................................................................................. 27 typical circuit connection ........................................................... 28 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 automotive products ................................................................. 30 revision history 11/13 rev. 0 to rev. a changes to features section and general description secti on ... 1 added figure 1; renumbered sequentially .................................. 3 changes to table 1 ............................................................................ 4 added pixel port timing specifications (adv728 2 only) section ................................................................................................ 9 added endnote 1; table 7 .............................................................. 1 0 added figure 6 and table 9 ........................................................... 1 1 changes to theory of operation section .................................... 1 3 changes to d vddio supply voltage section .................................. 15 changes to table 1 2 ........................................................................ 17 changes to programming the stb diagnostic function section .............................................................................................. 18 added itu - r bt.656 tx configuration (adv728 2 only) section .............................................................................................. 22 changes to register map s section ............................................... 25 chang es to power supply decoupling section and digit al outputs section .............................................................................. 27 changes to typical circuit connections section ...................... 28 changes to ordering guide .......................................................... 3 0 8 /13 revision 0: initial version
data sheet adv7282 rev. a | page 3 of 32 functional block dia grams xtalp xtaln a in 1 a in 2 a in 3 a in 4 differential or single-ended analog video inputs aa filter aa filter aa filter aa filter digital processing block 2d comb vbi slicer i2p color demod sclk diag1 diag2 sdata alsb reset pwrdwn 10-bit adc reference diagnostics pll adllt processing clock processing block i 2 c/control mux block fifo output block adv7282 sha + ? adc llc intrq ace down dither 1 1534-200 8-bit pixel data p0 to p7 figure 1. adv7282 functional block diagram xtalp xtaln a in 1 a in 2 a in 3 a in 4 a in 5 a in 6 differential or single-ended analog video inputs aa filter aa filter aa filter aa filter digital processing block 2d comb vbi slicer i2p color demod sclk diag1 diag2 sdata alsb reset pwrdwn 10-bit adc reference diagnostics pll adllt processing clock processing block i 2 c/control mux block fifo output block adv7282-m sha + ? adc clkp clkn d0p d0n intrq gpo0 gpo1 gpo2 ace down dither mipi tx 1 1534-001 figure 2. adv7282 - m functional block diagram
adv7282 data sheet rev. a | page 4 of 32 specifications electrical specifica tions a vdd , d vdd , p vdd , and m vdd = 1.71 v to 1.89 v , d vddio = 2.97 v to 3. 63 v , specified at operating tempe rature range, unless otherwise noted. note that m vdd only applies to the adv7282 - m . table 1 . parameter symbol test conditions/comments min typ max unit static performance adc resolution n 10 bits integral nonlinearity inl cvbs mode 2 lsb differential nonlinearity dnl cvbs mode 0.6 lsb digital inputs input high voltage v ih d vddio = 3.3 v 2 v d vddio = 1.8 v, adv7282 only 1.2 v input low voltage v il d vddio = 3.3 v 0.8 v d vddio = 1.8 v, adv7282 only 0.4 v input leakage current i in reset pin ? 10 +10 a sdata, sclk pins ? 10 +15 a pwrdwn , alsb pins ? 10 +50 a input capacitance c in 10 pf crystal input input high voltage v ih xtaln pin 1.2 v input low voltage v il xtaln pin 0.4 v digital outputs output high voltage v oh d vddio = 3.3 v, i source = 0.4 ma 2.4 v d vddio = 1.8 v, i source = 0.4 ma, adv7282 only 1.4 v output low voltage v ol d vddio = 3.3 v, i sink = 3.2 ma 0.4 v d vddio = 1.8 v, i sink = 1.6 ma, adv7282 only 0.2 v high impedance leakage current i leak 10 a output capacitance c out 20 pf power requirements 1 , 2 , 3 digital i/o power supply d vddio adv7282 - m 2.97 3.3 3.63 v adv7282 1.62 3.3 3.63 v pll power supply p vdd 1.71 1.8 1.89 v analog power supply a vdd 1.71 1.8 1.89 v digital power supply d vdd 1.71 1.8 1.89 v mipi tx power supply m vdd adv7282 - m only 1.71 1.8 1.89 v digital i/o supply current i dvddio adv7282 - m 1.5 ma adv7282 5 ma pll supply current i pvdd 12 ma mipi tx supply current i mvdd adv7282 - m onl y 14 ma analog supply current i avdd single - ended cvbs input 35 ma differential cvbs input fully differential and pseudo differential cvbs 69 ma y/c input 60 ma yprpb input 75 ma digital supply current i dvdd single - ended cv bs input 70 ma differential cvbs input fully differential and pseudo differential cvbs 70 ma y/c input 70 ma yprpb input 70 ma
data sheet adv7282 rev. a | page 5 of 32 parameter symbol test conditions/comments min typ max unit power - down currents 1 digital i/o supply power - down current i dvddio_pd 73 a pll supply power - down current i pvdd_pd 46 a analog supply power - down current i avdd_pd 0.2 a digital supply power - down current i dvdd_pd 420 a mipi tx supply power - down current i mvdd_pd 4.5 a total power dissipation in power - down mode 1 mw 1 guaranteed by characterization. 2 typical current consumption values are measur ed with nominal volta ge supply levels and an smpte bar test pattern. 3 all specifications apply when the i2p core is activated, unless otherwise stated. video specifications a vdd , d vdd , p vdd , and m vdd = 1.71 v to 1.89 v , d vddio = 2.97 v to 3. 63 v , specified at operating temperature range, unless otherwise noted. specifications guaranteed by characterization. note that m vdd o nly applies to the adv7282 - m . table 2 . parameter symbol test conditions/comments min typ max unit nonlinear specifications 1 differential phase dp cvbs input, modu lated 5 - step 0.9 degrees differential gain dg cvbs input, modulated 5 - step 0.5 % luma nonlinearity lnl cvbs input, 5 - step 2.0 % noise specifications signal -to - noise ratio, unweighted snr luma ramp 57.1 db luma flat field 58 db analo g front - end crosstalk 60 db common - mode rejectio n ratio 2 cmr r 7 3 db lock time specifications horizontal lock range ? 5 +5 % vertical lock range 40 70 hz f sc subcarrier lock range 1.3 khz color lock - in time 60 lines synchronization depth range 20 200 % color burst range 5 200 % vertical lock time 2 fields autodetection switch speed 3 100 lines fast switch speed 4 100 ms luma specifications cvbs, 1 v input luma brightness accuracy 1 % luma contrast accuracy 1 % 1 these specifications apply for all cvbs input types (ntsc, pal, and secam), as well as for single - ended and differential c vbs inputs. 2 the cmrr of this circuit design is critically dependent on the external resistor matching on the circuit inputs (see the input networks section). the cmrr measurement was performed with 0.1% tolerant resistors, a common - mode voltage of 1 v, and a common - mode frequency of 10 khz. 3 autodetection switch speed is the time required for the adv7282 / adv7282 - m to detect which video format is present at its input, for example, pal i or ntsc m. 4 fast switch speed is the time required for the adv7282 / adv7282 - m to switch from one analog input (single - ended or differential) to another, for example, switching from a in 1 to a in 2.
adv7282 data sheet rev. a | page 6 of 32 analog specification s a vdd , d vdd , p vdd , and m vdd = 1.71 v to 1.89 v, d vddio = 2.97 v to 3.63 v, specified at operating temperature range, unless otherwise noted. specifications guaranteed by characterization. note that m vdd only applies to the adv7282 - m . table 3 . parameter test conditions/comments min typ max unit clamp circuitry external clamp capacitor 0.1 f input impedance clamps switched off 10 m? large clamp source current 0.4 ma large clamp sink current 0.4 ma fine clamp source current 10 a fine clamp sink current 10 a clock and i 2 c timing specificati ons a vdd , d vdd , p vdd , and m vdd = 1.71 v to 1.89 v, d vddio = 2.97 v to 3.63 v, specified at operating temperature range, unless otherwise noted. specifications guaranteed by characterization. not e that m vdd only applies to the adv7282 - m . table 4 . parameter symbol min typ max unit system clock and crystal nominal frequency 28.63636 mhz frequency stabili ty 50 ppm i 2 c port sclk frequency 400 khz sclk minimum pulse width high t 1 0.6 s sclk minimum pulse width low t 2 1.3 s hold time (start condition) t 3 0.6 s setup time (start condition) t 4 0.6 s sdata setup time t 5 100 ns s clk and sdata rise times t 6 300 ns sclk and sdata fall times t 7 300 ns setup time (stop condition) t 8 0.6 s reset input reset pulse width 5 ms sdata sclk t 3 t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 1 1534-002 figure 3. i 2 c timing diagram
data sheet adv7282 rev. a | page 7 of 32 mipi video output sp ecifications ( adv7282 - m only) a vdd , d vdd , p vdd , and m vdd = 1.71 v to 1.89 v, d vddio = 2.97 v to 3.63 v, specified at operating temperature range, unless otherwise noted. th e csi - 2 clock lane of the adv7282 - m remains in high speed (hs) mode even when the data lane enters low power (lp) mode. for this reason, some measurements on the clock lane that pertain to low po wer mode are not applicable. unless otherwise stated, all high speed measurements were performed with the adv7282 - m operating in progressive mode and with a nominal 432 mbps output data rate. spe cifications guaranteed by characterization. table 5 . parameter symbol test conditions/comments min typ max unit unit interval ui interlaced output 4.63 ns progressive output 2.31 ns data lane lp tx dc specification s 1 thevenin output high level v oh 1.1 1.2 1.3 v thevenin output low level v ol ? 50 0 +50 mv data lane lp tx ac specifications 1 rise time, 15% to 85% 25 ns fall time, 85% to 15% 25 ns rise time, 30% to 85% 35 ns data lane lp slew rate vs. c load maximum slew rate o ver entire vertical edge region rising edge 150 mv/ns falling edge 150 mv/ns minimum slew rate 400 mv v out 930 mv falling edge 30 mv/ns 400 mv v out 700 mv rising edge 30 mv/ns 700 mv v out 930 mv rising edge >0 mv/ns pulse width of lp exclusive - or clock first clock pulse after stop state or last pulse before stop state 40 ns all other clock pulses 20 ns period of lp exc lusive - or clock 90 ns clock lane lp tx dc specifications 1 thevenin output high level v oh 1.1 1.2 1.3 v thevenin output low level v ol ? 50 0 +50 mv clock lane lp tx ac specifications 1 rise time, 15% to 85% 25 ns fall time, 85% to 15% 25 ns clock lane lp slew rate maximum slew rate o ver entire vertical edge region rising edge 150 mv/ns falling edge 150 mv/ns minimum slew rate 40 0 mv v out 930 mv falling edge 30 mv/ns 400 mv v out 700 mv rising edge 30 mv/ns 700 mv v out 930 mv rising edge >0 mv/ns data lane hs tx signaling requirements see figure 4 low power to high speed transition stage t 9 time that the d0p pin is at v ol and the d0n pin is at v oh 50 ns t 10 time that the d0p and d0n pins are at v ol 40 + (4 ui) 85 + (6 ui) ns t 11 t 10 plus the hs - zero period 145 + (10 ui) ns high speed differential voltage swing |v 1 | 140 200 270 mv p - p differential voltage mismatch 10 mv single - ended output high voltages 360 mv static common - mode voltage level 150 200 250 mv static common - mode voltage mismatch 5 mv dynamic common level variations 50 mhz to 450 mhz 25 mv above 450 mhz 15 mv
adv7282 data sheet rev. a | page 8 of 32 parameter symbol test conditions/comments min typ max unit rise time, 20% to 80% 0. 15 0.3 ui n s fall time, 80% to 20% 0.15 0.3 ui n s high speed to low power transition stage t 12 time that the adv7282 - m drives the flipped last data bit after sending the last payload data bit of an hs transmission burst 60 + (4 ui) ns t 13 post - end - of - transmission rise time (30% to 85%) 35 ns t 14 time from start of t 12 to start of low power st ate following an hs transmission burst 105 + (12 ui) ns t 15 time that a low power state is transmitted after an hs trans mis - sion burst 100 ns clock lane hs tx signaling requirements see figure 4 low power to high speed transition stage 2 time that the clkp pin is at v ol and the clkn pin is at v oh 50 ns time that the clkp and clkn pins are at v ol 38 95 ns clock hs - zero period 300 500 ns high speed differential voltage swing |v 2 | 140 200 270 mv p - p differential voltage mismatch 10 mv single - ended output high voltages 360 mv static common - mode voltage level 150 200 250 mv static common - mode voltage mismatch 5 mv dynamic common level variations 50 mhz to 450 mhz 25 mv above 450 mhz 15 mv rise time, 20% to 80% 0.15 0.3 ui ns fall time, 80% to 20% 0.15 0.3 ui ns hs tx clock to data lane timing requirements data to clock skew 0.35 ui 0.65 ui ns 1 these measurements were performed with c load = 50 pf. 2 t he clock lane remains in high speed m ode throughout normal operation. these results apply only to the adv7282 - m during startup. 11534-003 t 15 t 12 t 14 t 13 v oh v ol clkp/clkn t 11 t 10 t 9 d0p/d0n |v 2 | |v 1 | transmit first data bit low power to high speed transition start of transmission sequence high speed data transmission hs-zero hs-trail high speed to low power transition figure 4. adv7282 - m output timing diagram ( conforms with mipi csi - 2 specification)
data sheet adv7282 rev. a | page 9 of 32 pixel port timing specifications ( adv7282 only) a vdd , d vdd , and p vdd = 1.71 v to 1.89 v, d vddio = 1.62 v to 3.63 v, specified at operating temperature range, unless otherwise noted. specifications guaranteed by characterization. table 6. parameter symbol test conditions/comments min typ max unit clock outputs llc mark space ratio t 16 :t 17 45:55 55:45 % duty cycle data and control outputs data output transitional time t 18 negative clock edge to start of valid data (t setup = t 17 ? t 18 ) 3.8 ns t 19 end of valid data to negative clock edge (t hold = t 16 ? t 19 ) 6.9 ns output llc outputs p0 to p7 t 16 t 17 t 18 t 19 11534-201 figure 5. adv7282 pixel port and control output timing diagram
adv7282 data sheet rev. a | page 10 of 32 absolute maximum rat ings table 7 . parameter rating a vdd to dgnd 2.2 v d vdd to dgnd 2.2 v p vdd to dgnd 2.2 v m vdd to dgnd 1 2.2 v d vddio to dgnd 4 v p vdd to d vdd ? 0. 9 v to +0.9 v m vdd to d vdd 1 ? 0. 9 v to +0.9 v a vdd to d vdd ? 0. 9 v to +0.9 v digital inputs voltage dgnd ? 0.3 v t o d vddio + 0.3 v digital outputs voltage dgnd ? 0.3 v to d vddio + 0.3 v analog inputs to ground ground ? 0.3 v to a vdd + 0.3 v maximum junction temperature (t j max) 140c storage temperature range ? 65c to +150c infrared reflow soldering (20 sec) 26 0c 1 m vdd applies to the adv7282 - m only. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance integrated circuit with an esd rating of <2 kv, and it is esd sensitive. proper precautions must be taken for handling and assembly. thermal resistance the thermal resistance values in table 8 are spec ified for the device soldered onto a 4 - layer printed circuit board (pcb) with a common ground plane and with the exposed pad of the device connected to dgnd. the values in table 8 are maximum values. table 8 . thermal resistance for the 32 - lead lfcsp thermal characteristic symbol value unit junction -to - ambient thermal resistance (still air) ja 32.5 c/w junction -to - case thermal resistance jc 2.3 c/w reflow solder the adv7282 / adv7282 - m is a pb - free, environmentally friendly product. it is manufactured using the most up - to - date materials and processes. the coating on t he leads of each device is 100% pure sn electroplate. the device is suitable for pb - free applications and can withstand surface - mount soldering at up to 255c ( 5c). in addition, the adv7282 / adv7282 - m is backward - compatible with conventional snpb soldering processes. this means that the electroplated sn coating can be soldered with sn/pb solder pastes at conventional reflow temperatu res of 220c to 235c. esd caution
data sheet adv7282 rev. a | page 11 of 32 pin configuration and fu nction descriptions 24 a in 3 23 diag2 22 diag1 21 a vdd 20 vrefn 19 vrefp 18 a in 2 17 a in 1 1 2 3 4 5 6 7 8 dgnd d vddio d vdd dgnd p7 p6 p5 p4 9 10 11 12 13 14 15 16 p3 p2 p1 p0 d vdd xtalp xtaln p vdd 32 31 30 29 28 27 26 25 llc pwrdwn sclk sdata alsb reset intrq a in 4 adv7282 top view (not to scale) notes 1. the exposed pad must be connected to dgnd. 11534-202 figure 6. pin configuration, adv7282 table 9. pin function descriptions, adv7282 pin no. mnemonic type description 1, 4 dgnd ground ground for digital supply. 2 d vddio power digital i/o power supply (1.8 v or 3.3 v). 3, 13 d vdd power digital power supply (1.8 v). 5 to 12 p7 to p0 output video pixel output ports. 14 xtalp output connect this pin to the external 28.63636 mhz crys tal, or leave it unconnected if an external 1.8 v, 28.63636 mhz clock oscillator source is used to clock the adv7282 . the crystal used with the adv7282 must be a fundamental crystal. 15 xtaln input input pin for the external 28.63636 mhz crystal. the crystal used with the adv7282 must be a fundamental crystal. if an external 1.8 v, 28.63636 mhz clock oscillator source is used to clock the adv7282 , the output of the oscillator is fed into the xtaln pin. 16 p vdd power pll power supply (1.8 v). 17, 18, 24, 25 a in 1 to a in 4 input analog video input channels. 19 vrefp output internal voltage reference output. 20 vrefn output internal voltage reference output. 21 a vdd power analog power supply (1.8 v). 22 diag1 input diagnostic input 1. 23 diag2 input diagnostic input 2. 26 intrq output interrupt request output. an interrupt occurs when certain signals are detected on the input video. 27 reset input system reset input (active low). a minimum low reset pulse width of 5 ms is required to reset the adv7282 circuitry. 28 alsb input this pin selects the i 2 c write address for the adv7282 . when alsb is set to logic 0, the write address is 0x40; when alsb is set to logic 1, the write address is 0x42. 29 sdata input/output i 2 c port serial data input/output. 30 sclk input i 2 c port serial clock input. the maximum clock rate is 400 khz. 31 pwrdwn input power-down pin. a logic low on this pin places the adv7282 in power-down mode. 32 llc output line-locked output clock for output pixel data. the clock output is nominally 27 mhz, but it increases or decreases according to the video line length. epad (ep) exposed pad. the expo sed pad must be connected to dgnd.
adv7282 data sheet rev. a | page 12 of 32 24 a in 4 23 a in 3 22 diag1 21 a vdd 20 vrefn 19 vrefp 18 a in 2 17 a in 1 1 2 3 4 5 6 7 8 dgnd d vddio d vdd dgnd intrq gpo2 gpo1 gpo0 9 10 11 12 13 14 15 16 d0p d0n clkp clkn m vdd xtalp xtaln pvdd 32 31 30 29 28 27 26 25 pwrdwn sclk sdata alsb reset a in 6 a in 5 diag2 adv7282-m top view (not to scale) notes 1. the exposed pad must be connected to dgnd. 11534-004 figure 7. pin configuration, adv7282-m table 10. pin function descriptions, adv7282-m pin no. mnemonic type description 1, 4 dgnd ground ground for digital supply. 2 d vddio power digital i/o power supply (3.3 v). 3 d vdd power digital power supply (1.8 v). 5 intrq output interrupt request output. an interrupt occurs when certain signals are detected on the input video. 6 to 8 gpo2 to gpo0 output general-purpose outputs. these pins can be configured via i 2 c to allow control of external devices. 9 d0p output positive mipi differential data output. 10 d0n output negative mipi differential data output. 11 clkp output positive mipi differential clock output. 12 clkn output negative mipi differential clock output. 13 m vdd power mipi digital power supply (1.8 v). 14 xtalp output connect this pin to the external 28.63636 mhz crys tal, or leave it unconnected if an external 1.8 v, 28.63636 mhz clock oscillator source is used to clock the adv7282-m . the crystal used with the adv7282-m must be a fundamental crystal. 15 xtaln input input pin for the external 28.63636 mhz crystal. the crystal used with the adv7282-m must be a fundamental crystal. if an external 1.8 v, 28.63636 mhz clock oscillator source is used to clock the adv7282-m , the output of the oscillator is fed into the xtaln pin. 16 p vdd power pll power supply (1.8 v). 17, 18, 23, 24, 26, 27 a in 1 to a in 6 input analog video input channels. 19 vrefp output internal voltage reference output. 20 vrefn output internal voltage reference output. 21 a vdd power analog power supply (1.8 v). 22 diag1 input diagnostic input 1. 25 diag2 input diagnostic input 2. 28 reset input system reset input (active low). a minimum low reset pulse width of 5 ms is required to reset the adv7282-m circuitry. 29 alsb input this pin selects the i 2 c write address for the adv7282-m . when alsb is set to logic 0, the write address is 0x40; when alsb is set to logic 1, the write address is 0x42. 30 sdata input/output i 2 c port serial data input/output. 31 sclk input i 2 c port serial clock input. the maximum clock rate is 400 khz. 32 pwrdwn input power-down pin. a logic low on this pin places the adv7282-m in power-down mode. epad (ep) exposed pad. the expo sed pad must be connected to dgnd.
data sheet adv7282 rev. a | page 13 of 32 theory of operation the adv7282 / adv7282 - m are versatile one - chip, multiformat video decoder s . the adv7282 / adv7282 - m automatically detect standard analog baseband video signals compatible with worldwide ntsc, pal, and secam standards in the form of composite, s - video, and component video . the adv7282 converts the analog video signals into an 8 - bit ycrcb 4:2:2 video data stream that is compatible with the 8 - bit itu - r bt.656 interface standard. the adv72 82- m converts the analog video signals into an 8 - bit ycrcb 4:2:2 video data stream that is output over a mipi csi - 2 interface. th e mipi csi - 2 output interface connect s to a wide range of video processors and fpgas. the accurate 10 - bit analog - to - digital co nversion provides professional quality video performance for consumer applications with true 8 - bit data resolution. the analog video inputs of the adv7282 / adv7282 - m accept single - ended, pseudo differential, and fully differential composite video signals, as well as s - video and yprpb video signals, supporting a wide range of consumer and automotive video sources. in differential cvbs mo de , the adv7282 / adv7282 - m , along with an external resistor divider , provides a common - mode input range of up to 4 v , enabling the re moval of large signal , common - mode transients present on the video lines. the advanced interlaced - to - progressive (i2p) function allows the adv7282 / adv7282 - m to convert an interlaced video input into a progressive video output. this function is per - formed without the need for external memory. the adv7282 / adv7282 - m uses edge adaptive technology to minimize video defects on low angle lines. the automatic gain control ( agc ) and clamp restore circuitry allows an input video signal peak - to - peak range of 0 v to 1.0 v at the analog video input pins of the adv7282 / adv7282 - m . alternatively, the agc and clamp restore circuitry can be bypassed for manual settings. ac coupling of the input video signals provides short - to - battery (stb) protection. stb diagnostics can be performed on two input video signals. the adv7282 / adv7282 - m support a number of other functions , including 8 - bit to 6 - bit down dither mode and adaptive contrast enhancement (ace). the adv7282 / adv7282 - m are programmed via a 2 - wire, serial bidirectional port (i 2 c compatible) and is fabricated in a 1.8 v cmos process. the monolithic cmos construction of the adv7282 / adv7282 - m ensures greater functionality with lower power dissipation. the lfcsp package option makes the decoder ideal for space - constrained portable applications. analog front end (afe) the analog front end (afe) of the adv7282 / adv7282 - m comprises a single high speed, 10 - bit adc that digitizes the an alog video signal before applying it to the standard definition processor (sdp). the afe uses differential channels to the adc to ensure high performance in mixed - signal applications and to enable differ ential cvbs inputs to be connected directly to the adv7282 / adv7282 - m . the afe also includes a n input mux that enables multiple video signals to be applied to the adv7282 / adv7282 - m . the input mux allows u p to four composite video signals to be applied to the adv7282 and up to six composite video signals to be applied to the adv7282 - m . current clamps are positioned in front of the adc to ensure that the video signal remains within the range of th e converter. a resistor divider network is required before each analog input channel to ensure that the input signal is kept within the range of the adc (see the input networks section) . fine clamping of the video signal is performed downstream by digital fine clamp - ing within the adv7282 / adv7282 - m . tab le 11 lists the three adc clock rates that are determined by the video input format to be processed. these clock rates ensure 4 oversampling per channel for cvbs, y/c, and yprpb modes. table 11 . adc clock rates input format adc cl ock rate (mhz) 1 oversampling rate per channel cvbs 57.27 4 y/c (s - video) 114 4 yprpb 172 4 1 based on a 28.63636 mhz crystal between the xtalp and xtaln pins. the fully differential afe of the adv7282 / adv7282 - m provides inherent small and large signal no ise rejection, improved electro magnetic interference (emi) protection, and the ability to absorb ground bounce. support is pr ovided for both true differential and pseudo differential signals.
adv7282 data sheet rev. a | page 14 of 32 standard definition processor (sdp) the adv7282 / adv7282 - m is capable of decoding a large selection of baseband video signals in composite (both single - ended and differential), s - video, and component formats. the video standards supported by the video processor include ? pal b, pal d, pal g, pal h, pal i, pal m, pa l n, pa l nc, pa l 60 ? ntsc j, ntsc m, ntsc 4.43 ? secam b, secam d, secam g, secam k, secam l using the standard definition processor (sdp), the adv7282 / adv7282 - m can automatically detect the video standard and process it accordingly. the adv7282 / adv7282 - m has a five - lin e a daptive 2d comb filter that provides superior chrominance and luminance separation when decoding a composite video signal. this highly adaptive filter automatically adjusts its processing mode accord - ing to the video standard and signal quality without user intervention. video user controls such as brightness, contrast, saturation, and hue are also available with the adv7282 / adv728 2 - m . the adv7282 / adv7282 - m implements the patented adaptive digital line length tracking (adllt?) algorithm to track varying video line lengths from sources such as vcrs. adllt enables the adv7282 / adv7282 - m to track and decode poor quality video sources such as v crs and noisy sources from tuner outputs and camcorders. the adv7282 / adv7282 - m contains a chroma transient improvement (cti) process or that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. adaptive contrast enhancement (ace) offers improved visual detail using an algorithm that automatically varies contrast levels to enhance picture detail. ace i ncreas es the contrast in dark areas of an image without saturating the bright areas of the image. this feature is particularly useful in automotive applications, where it can be important to discern objects in shaded areas. down dithering converts the outp ut of the adv7282 / adv7282 - m from an 8 - bit to a 6 - bit output, enabl ing ease of design for standard lcd panels. the i2p block conver ts the interlaced video input into a pro - gress sive video output without the need for external memory. the sdp can process a variety of vbi data services, such as closed captioning (ccap), wide screen signaling (wss), copy generation management system (cgms ), and teletext data slicing for world s ystem teletext (wst). vbi d ata is transmitted via the mipi csi - 2 link as ancillar y data packets. the adv7282 / adv7282 - m is fully rovi? (macrovision?) c ompliant ; d etec tion circuitry enables type i, type ii, and type iii protection levels to be identified and reported to the user. the decoder is also fully robust to all macrovision signal inputs.
data sheet adv7282 rev. a | page 15 of 32 power supply sequenc ing optimal power - up sequence the optim al power - up sequence for the adv7282 / adv7282 - m is to first power up the 3.3 v d vddio supply, followed by the 1.8 v supplies (d vdd , p vdd , a vdd , and m vdd ). note that m vdd only applies to the adv7282 - m . when powering up the adv7282 / adv7282 - m , follow these steps. during power - up, all supplies must adhere to the specifications listed in the absolute maximum ratings section. 1. a ssert the pwrdwn and reset pins (pull the pins low) . 2. power up the d vddio supply. 3. a fter d vddio is fully asserted , power up the 1.8 v supplies . 4. a fter the 1.8 v supplies are fu lly asserted, pull the pwrdwn pin high . 5. wait 5 ms and then pull the reset pin high. 6. after all power supplies and the pwrdwn and reset pins are powe red up and stable, wait an additional 5 ms before initiating i 2 c communication with the adv7282 - m . simplified power - up sequence alternatively, t he adv7282 / adv7282 - m can be powered up by asserting all supplies and the pwrdwn and reset pins simultaneously. after this operation, perform a s oftware reset, then wait 10 ms before initiating i 2 c communication with the adv7282 / adv7282 - m . w hile the supplies are being establis hed , take care to ensure that a lower rated supply does not go above a higher rated supply level . during power - up, all supplies must adhere to the specifications listed in the absolute maximum ratings section. power - d own s equenc e the adv7282 / adv7282 - m supplies can be deasserted simultaneously as long as d vddio does not go below a lower rated supply. d vddio s upply voltage for correct operation of the adv7282 - m , the d vddio supply must be from 2.97 v to 3.63 v. the adv7282 however, can ope rate with a nominal d vddio voltage of 1.8 v. in this case, apply the power - up sequences described previously . the only change is that d vddio is powered up to 1.8 v instead of 3.3 v. note that when the adv7282 operates with a nominal d vddio voltage of 1.8 v, t h e n set the drive strength of all digital outputs to a maximum. note that when d vddio is 1.8 v, pull the i 2 c pins of the adv72 82 (sclk and sdata) up to 1.8 v. under normal circumstances, the i 2 c pins of the adv7282 should be pulled up to 3.3v. 3.3v 1.8v voltage time 3.3v supply power-up 1.8v supplies power-up 3.3v supply pwrdwn pin pwrdwn pin power-up reset pin power-up reset pin 1.8v supplies 5ms reset operation 5ms wait 1 1534-005 figure 8. optimal power - up sequence
adv7282 data sheet rev. a | page 16 of 32 input networks an input network (e xternal resistor and capacitor circuit ) is required on the a in x input pins of the adv7282 / adv7282 - m . th e com ponents of the input network d epend on the video format selected for the analog input. single - ended input network figure 9 shows the input network to use on each a in x input pin of the adv7282 / adv7282 - m when any of the following video input formats is used: ? single - ended cvbs ? yc (s - video) ? yprpb 51 a in 3 input connector video input from source 24 100nf ext esd 11534-006 figure 9 . single- en ded input network the 24 ? and 51 ? resistors supply the 75 ? end termination required for the analog video input. these resistors also create a resistor divider with a gain of 0.68 . t he resistor divider attenuates the amplitude of the input analog video a nd scales the input to the adc range of the adv7282 / adv7282 - m . this allows an input range to the adv7282 / adv7282 - m of u p to 1.4 7 v p - p. note that amplifiers within the adc restore the amplitud e of the input signal so that signal - to - noise ratio (snr) performance is maintained. the 100 nf ac coupling capacitor removes the dc bias of the analog input video before it is fed into the a in x pin of the adv7282 / adv7282 - m . the clamping circuitry within the adv7282 / adv7282 - m restores the dc bias of the input signal to the optimal l evel before it is fed into the adc of the adv7282 / adv7282 - m . differential input n etwork fi gure 10 shows the input network to use when differential cvbs video is input on the a in x input pins of the adv7282 / adv7282 - m . a in 1 a in 2 input connector input connector video input from source ext esd r1 1.3k 100nf 1.3k 100nf 430? 430? 1 1534-007 f igure 10 . differential input network fully differential video transmission involves transmitting two complementary cvbs signals. pseudo differential video transmission involves transmitting a cvbs sig nal and a source ground signal . differential video transmission has several key advantages over single - ended transmission, including the following: ? inherent small signal and large signal noise rejection ? improved emi performance ? ability to absorb ground bounce resistor r1 provides the r f end termination for the differential cvbs input lines. for a pseudo differential cvbs input, a value of 75 ? is recommended for r1. for a fully differential cvbs input, a value of 150 ? is recommended for r1. the 1.3 k? and 430 ? resistors create a resis tor divider with a gain of 0.25 . t he resistor divider attenu ates the amplitude of the input analog video , but increases the input common - mode range of the adv7282 / adv7282 - m to 4 v p - p . note that amplifiers within the adc restore the amplitude of the input signal so that snr performance is maintained. the 100 nf ac coupling capacitor removes the dc bias of the analog input video before it is fed into the a in x pin of the adv7282 / adv7282 - m . the clamping circuitry within the adv7282 / adv7282 - m restores the dc bias of the input signal to the optimal level before it is fed into the adc of the adv7282 / adv7282 - m . the combination of the 1.3 k? and 430 ? resistors and the 100 nf ac coupling capacitor s limit s the current flow into the adv7282 / adv7282 - m durin g short - to - battery (stb) events (see the short - to - battery protection section). t o achi eve optimal performance , the 1.3 k? and 430 ? resistors must be c losely matched ; that is, all 1.3 k? and 430 ? resistors must have the same resistance tolerance , and this tolerance must be as low as possible. short - to - battery protection in differential mode, t he adv7282 / adv7282 - m is protected against short - to - battery (stb) events by ac coupling capacitors (see figure 10 ). the input networ k resistors are sized to reduce the current flow during an stb event, thus preventing damage to the resistors. the r1 resistor is protected because no current or limited current flows through it during an stb event. the adv7282 / adv7282 - m provides two stb diagnostic pins that can be used to generate an interrupt when an stb event occurs. for more information, see the short - to - battery (stb) diagnostics section.
data sheet adv7282 rev. a | page 17 of 32 input configuration the input format of the adv7282 / adv7282 - m is specified using the insel [4:0] bits (see table 12) . the se bits also configure the sdp core to process cvbs, differential cvbs, y/c (s - video ), or com ponent (yprpb) format . the insel[4:0] bits are located in the user sub map of t he register space at address 0x00[4:0]. for more information about the registers, see the register maps section. the insel[4:0] bits specify predefined analog input routing schemes , eliminating the need for manual mux programming and allow ing the user to route the various video signal types to the decoder. for example, if the cvbs input is selected, the remaining channels are powered down. table 12 . input format specified by the insel[4:0] bits insel[4:0] bit value video format analog inputs adv7282 adv7282 - m 00000 cvbs cvbs input on a in 1 cvbs input on a in 1 00001 cvbs cvbs input on a in 2 cvbs input on a in 2 00010 cvbs reserved cvbs input on a in 3 00011 cvbs reserved cvbs input on a in 4 00100 reserved reserved reserved 00101 reserved reserved reserved 00110 cvbs cvbs input on a in 3 cvbs input on a in 5 00111 cvbs cv bs input on a in 4 cvbs input on a in 6 01000 y/c (s - video) y input on a in 1; c input on a in 2 y input on a in 1; c input on a in 2 01001 y/c (s - video) reserved y input on a in 3; c input on a in 4 01010 reserved reserved reserved 01011 y/c (s - video) y input on a in 3; c input on a in 4 y input on a in 5; c input on a in 6 01100 yprpb reserved 1 y input on a in 1; pb input on a in 2; pr input on a in 3 01101 reserved reserved reserved 01110 differential cvbs positive input on a in 1; negative input on a in 2 positive input on a in 1 ; negative input on a in 2 01111 differential cvbs reserved positive input on a in 3; negative input on a in 4 10000 reserved reserved reserved 10001 differential cvbs positive input on a in 3; negative input on a in 4 positive input on a in 5; negative input on a in 6 10010 to 11111 reserved reserved reserved 1 note that it is possible for the adv7282 to receive ypbpr formats; however, a manual muxing scheme is required. in this case luma(y) is fed in on a in 1 or a in 3, blue chroma (pb) is fed in on a in 4, and red chroma (pr) is fed in on a in 2.
adv7282 data sheet rev. a | page 18 of 32 short - to - battery ( stb ) diagnostics the adv7282 / adv7282 - m senses an stb event via t he diag1 and diag2 pins. the diag1 and diag2 pins can sense an stb event on either the positive or negative differential input because of the negligible voltage drop across resistor r1. a in 1 a in 2 input connector input connector video input from source ext esd diag1 r1 1.3k 100nf 1.3k 100nf 430? r4 r5 430? 11534-008 figure 11 . diagnostic connections resistors r4 and r5 divide down the voltage at the input con - nector to protect the diag x pin from a n stb event. the diag x pin circuitry compares this voltage to a programmable reference voltage, known as the diagnostic slice level. when the diagnostic slice level i s exceeded, an stb event has occurred . when the diag x pin voltage exceeds the diagnostic slice level voltage, a hardware interrupt is triggered and indicated by the intrq pin. a read back register is also provided, which allows the us er to determine the diag x pin on which the stb event occurred. use equation 1 to find the trigger voltage for a s elected diagnostic slice level. el _slice_lev diagnostic r5 r4 r5 v trigger stb + = _ (1) where : v stb _ trigger is the minimum voltage required at the input connector to trig ger the stb interrupt on the adv7282 / adv7282 - m . diagnostic_slice_level is the programm able reference voltage. programming the stb d iagnostic function by default, the stb diagnostic function is disabled on the adv7282 / adv7282 - m . to enable the diagnostic function, follow the instructions in this section. diag1 pin diag1_sicer_prdn, user s map, address 0x5d[6] this bit powers up or powers down the diagnostic circuitry for the diag1 pin. table 13 . diag1_slicer_pwrdn function diag1_slicer_ pwrdn diagnostic slice level 0 power up the diagnostic circuitry for the diag1 pin. 1 (default) power down the d iagnostic c ircuitry for the diag1 pin. diag1_slice_level[2:0], user sub map, address 0x5d[4:2] the diag1_slice_level[2:0] bits allow the user to set the diagnostic slice level for the diag1 pin. when a voltage greater than the diagnostic slice level is seen on the diag1 pin, an stb interrupt is triggered. in order for the diagnostic slice level to be set correctly, the diagnostic circuitry for the diag1 pin must be powered up (see table 13). table 14 . diag1_slice_level[2:0] settings diag1_slice_level[2:0] diagnostic slice level 000 75 mv 001 225 mv 010 375 mv 011 (default) 525 mv 100 675 mv 101 825 mv 110 975 mv 111 1.125 v
data sheet adv7282 rev. a | page 19 of 32 diag2 pin diag2_ slicer_pwrdn, user sub map, address 0x5e[6] this bit powers up or powers down the diagnostic circuitry for the diag2 pin. table 15 . diag2_slicer_pwrdn function diag2_slicer_pwrdn diagnostic slice level 0 power up the diagnostic circuitry for the diag2 pin. 1 (default) power down the diagnostic circuitry for the diag2 pin. diag2_slice_level[2:0], user sub map, address 0x5e[4:2] the diag2_slice_level[2:0] bits a llow the user to set the diagnostic slice level for the diag2 pin. when a voltage greater than the diagnostic slice level is seen on the diag2 pin, an stb interrupt is triggered. in order for the diagnostic slice level to be set correctly, the diagnostic c ircuitry for the diag2 pin must be powered up (see table 15). table 16 . diag2_slice_level[2:0] settings diag2_slice_level[2:0] diagnostic slice level 000 75 mv 001 225 mv 010 375 mv 011 (default) 525 mv 100 675 mv 101 825 mv 110 975 mv 111 1.125 v
adv7282 data sheet rev. a | page 20 of 32 adaptive contrast en hancement (ace) the adv7282 / adv7282 - m c an increase the contrast of an image depend ing on the content of the picture , allowing bright areas to be made brighter and dark areas to be made darker. t he optional ace feature enables the contrast within dark areas to be increased without significantly affecting the bright areas. the ace feature is particularly useful in automotive applications, where it can be important to discern objects in shaded areas . the ace function is disabled by default. to enable the ace function, execute the register writes sh own in table 17. to disabl e the ace function, execute the register writes shown in table 18. table 17. register writes to enable the ace function register map register address register write description user sub map (0x40 or 0x42) 0x0e 0x40 enter user sub map 2 user sub map 2 (0x40 or 0x42) 0x80 0x80 enable ace user sub map 2 (0x40 or 0x42) 0x0e 0x00 re enter u ser s ub m ap table 18. register writes to disable the ace function register map register address register write description user sub map (0x40 or 0x42) 0x0e 0x40 enter user sub map 2 user sub map 2 (0x40 or 0x42) 0x80 0x00 disable ace user sub map 2 (0x40 or 0x42) 0x0e 0x00 reenter user sub map
data sheet adv7282 rev. a | page 21 of 32 i2p function the advanced interlaced - to - progressive (i2p) function allows the adv7282 / adv7282 - m to convert an interlaced video input into a progressive video output. this function is performed without the need for external memory. the adv7282 / adv7282 - m use edge adaptive technology to minimize vi deo defects on low angle lines. the i2p f unction is disabled by default. to enable the i2p func - tion, use the recommended scripts from analog devices , inc .
adv7282 data sheet rev. a | page 22 of 32 itu - r bt.656 t x configuration ( adv7282 only) the adv7282 receives analog video and outputs digital video according to the itu - r bt.656 specification. the adv7282 outputs the itu - r bt.656 video data stream over the p0 to p7 data pins and has a line - locked clock (llc) pin . video data is output over the p0 to p7 pins in ycrcb 4:2:2 format. synchronization signals are automaticall y embedded in the video data signal in accordance with the itu - r bt.656 specification. the llc output is used to clock the output data on the p0 to p7 pins at a nominal frequency of 27 mhz. 11534-018 p0 p1 itu-r bt.656 data stream video decoder analog video input p2 p3 p4 p5 p6 p7 llc adv7282 standard definition processor analog front end figure 12 . itu - r bt.656 output stage of the adv7282
data sheet adv7282 rev. a | page 23 of 32 mipi csi-2 output ( adv7282-m only) the decoder in the adv7282-m outputs an itu-r bt.656 data stream. the itu-r bt.656 data stream is connected into a csi-2 tx module. data from the csi-2 tx module is fed into a d-phy physical layer and output serially from the device. the output of the adv7282-m consists of a single data channel on the d0p and d0n lanes and a clock channel on the clkp and clkn lanes. video data is output over the data lanes in high speed mode. the data lanes enter low power mode during the horizontal and vertical blanking periods. the clock lanes are used to clock the output video. after the adv7282-m is programmed, the clock lanes exit low power mode and remain in high speed mode until the part is reset or powered down. the adv7282-m outputs video data in an 8-bit ycrcb 4:2:2 format. when the i2p core is disabled, the video data is output in an interlaced format at a nominal data rate of 216 mbps. when the i2p core is enabled, the video data is output in a progressive format at a nominal data rate of 432 mbps (see the i2p function section for more information). d0p (1 bit) d0n (1 bit) clkp (1 bit) clkn (1 bit) itu-r bt.656 data stream csi-2 tx video decoder d-phy tx analog video input csi tx data output (8 bits) data lane lp signals (2 bits) clock lane lp signals (2 bits) 11534-009 figure 13. mipi csi-2 output stage of the adv7282-m
adv7282 data sheet rev. a | page 24 of 32 i 2 c port description the adv7282 / adv7282 - m supports a 2 - wire, i 2 c - compatible serial interface. two inputs, serial data (sdata) and serial clock (sclk), carry information between the adv7282 / adv7282 - m and the system i 2 c master controller. the i 2 c port of the adv7282 / adv7282 - m allows the user to set up and configure the decoder and to read back captured vbi data. the adv7282 / adv7282 - m has a number of possible i 2 c slave address es and sub address es ( see the register maps section). the main map of the adv7282 / adv7282 - m has four possible slave addresses for read and write operations, depending on the logic level of the alsb pin (see table 19) . table 19. main map i 2 c a ddress for the adv7282 -m alsb pin r/ w bit slave address 0 0 0x40 (write) 0 1 0x41 (read) 1 0 0x42 (write) 1 1 0x43 (read) the alsb pin controls bit 1 of the slave address. by changing the logic level of the alsb pin, it is possible to control two adv7282 / adv7282 - m devices in an application without usin g the same i 2 c slave address. the lsb (bit 0) s pecifies either a read or write operation : logic 1 corresponds to a read operation, and logic 0 corresponds to a write operation. to control the device on the bus, a specific protocol is followed. 1. t he master i nitiates a data transfer by establishing a start condition, which is defined as a high to low transition on sdata while sclk remains high , and indicates that an address/ data stream follows. 2. all peripherals respond to the start condition and shift the next eight bits (the 7 - bit address plus the r/ w bit). the bits are transferred from msb to lsb. 3. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse; th is is known as an acknowledge (ack) bit. 4. all other devices withdraw from the bus and maintain an idle condition. in t he idle condition , the device monitors the sdata and sclk lines for the start condition and t he correct transmitted address. the r/ w bit determines the direction of the data. logic 0 on the lsb of the first byte means that the master writes information to the peripheral. logic 1 on the lsb of the first byte means that the master reads i nformation from the peripheral. the adv7282 / adv7282 - m acts as a standard i 2 c slave device on the bus. the data on the sdata pin is eight bits long, supporting the 7 - bit address plus the r/ w bit. the device has subaddresses to enable access to the internal registers ; therefore, it interprets the first byte as the device address and the second byte as the starting subaddress. the subaddresses auto - incremen t, allowing data to be written to or read from the starting subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register individually with out updating all the registers. stop and start condi tions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. during a given sclk high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the adv7282 / adv7282 - m does not issue an acknowledge and returns to the idle condition. if the highest subaddress is exceeded in auto - increment mode, one of the following action s is taken: ? in read mode, the register contents of the highest sub - address continue to be output until the master device issues a no acknowledge , which indicates the end of a read. a no acknowledge condition occurs when the sdata line is not pulled low on the ninth pulse. ? in write mode, the data for the i nvalid byte is not loaded into a subaddress register. a no acknowledge is issued by the adv7282 / adv7282 - m , and the part returns to t he idle condition. sdata sclk start addr ack ack data ack stop subaddress 1?7 1?7 8 9 8 9 1?7 8 9 s p r/w 1 1534-010 figure 14 . bus data transfer s write sequence slave addr a(s) subaddress a(s) data a(s) data a(s) p s read sequence slave addr slave addr a(s) subaddress a(s) s a(s) data a(m) data a(m) p s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a(s) = no acknowledge by slave a(m) = no acknowledge by master lsb = 1 lsb = 0 1 1534-0 1 1 figure 15 . read and write sequence
data sheet adv7282 rev. a | page 25 of 32 register maps the adv7282 contains two register maps: the main register map and the vpp register map. the adv7282 - m contains three r egister m aps: the main register map, the v p p register map , and the csi register map (s ee figure 16) . note that the main map of the adv7282 / adv7282 - m contains three sub maps: user sub map, interrupt /vdp map and user sub map 2. main map the i 2 c slave address of the m ain map of the adv7282 / adv7282 - m is set by the alsb pin (see table 19 ). the main map allows the user to program the i 2 c slave addres se s of the vpp and csi maps. the main map contains three sub maps: the user sub map, the i nter rupt/vdp sub map , and user sub map 2 . these three sub maps a re accessed by writing to the sub_usr_en bits (address 0x0e[6:5]) within the main map (see figure 16 and table 20). user sub map the user sub map contains registers that p rogram the analog front end and digital core of the adv7282 / adv7282 - m . the user sub map has the same i 2 c slave address as the main m ap. to access the user sub map, set the sub_usr_en bits in the main map (address 0x0e[6:5] ) to 00. interrupt / vdp sub map the i nterrupt/vdp sub map contains registers that can be used to program internal interrupts, control the intrq pin , and decode v ertical b lanking i nterval (vbi) d ata. the interrupt/vdp sub map has the same i 2 c slave address as the main map. to access the interrupt/vdp sub map, set the sub_usr_en bits in the main map (address 0x0e[6:5]) to 01. user sub map 2 u ser s u b m ap 2 contains registers that control the ace, down dither , and fast lock functions. it also contains controls that set the acceptable input luma and chroma limits before the adv7282 / adv7282 - m enters free run and color kill modes. user sub map 2 has the same i 2 c slave address as the main map. to access user sub map 2, set the sub_usr_en bits in the main map (address 0x0e[6:5]) to 10 . vpp map device address write: 0x84 read: 0x85 (recommended settings) vpp map device address is programmable and set by register 0xfd in the user sub map csi map device address (recommended settings) write: 0x88 read: 0x89 csi map address is programmable and set by register 0xfe in the user sub map main map device address alsb pin high write: 0x42 read: 0x43 alsb pin low write: 0x40 read: 0x41 0x0e[6:5] = 00 user sub map 0x0e[6:5] = 01 interrupt/vdp sub map 0x0e[6:5] = 10 user sub map 2 11534-012 notes 1. csi map only applies to the adv7282-m model. figure 16 . register map and sub map access
adv7282 data sheet rev. a | page 26 of 32 table 20. i 2 c register map and sub map addresses alsb pin r/ w bit slave address sub_usr_en bits (address 0x0e[6:5] ) register map or sub map 0 0 (write) 0x40 00 user sub map 0 1 (read) 0x41 00 user sub map 0 0 (write) 0x40 01 interrupt/vdp sub map 0 1 (read) 0x41 01 interrupt/vdp s ub map 0 0 (write) 0x40 10 user sub map 2 0 1 (read) 0x41 10 user sub map 2 1 0 (write) 0x42 00 user su b map 1 1 (read) 0x43 00 user sub map 1 0 (write) 0x42 01 interrupt/vdp sub map 1 1 (read) 0x43 01 interrupt/vdp sub map 1 0 (write) 0x42 10 user sub map 2 1 1 (read) 0x43 10 user sub map 2 x 1 0 (write) 0x84 xx 1 vpp map x 1 1 (read) 0x85 xx 1 vpp map x 1 0 (write) 0x88 xx 1 csi map ( adv7282 -m o nly) x 1 1 (read) 0x89 xx 1 csi map ( adv7282 -m o nly) 1 x and xx mean dont care. vpp map the video postprocessor (vpp) map contains registers that control the i2p core (interlaced - to - progressive converter). the vpp map has a programmable i 2 c slave address, which is programmed using register 0xfd in the user sub map of the main map. the defaul t value for the vpp map address is 0x00; however, the vpp map cannot be accessed until the i 2 c slave address is reset. the recommended i 2 c slave address for the vpp map is 0x84 . to reset the i 2 c slave address of the vpp map, write to the vpp_slave_address[ 7:1] bits in the main register map (address 0xf d [7:1]). set these bits to a value of 0x84 (i 2 c write address; i 2 c read address is 0x85). csi map ( adv7282 - m only) the csi map contains registers t hat control the mipi csi - 2 output stream from the adv7282 - m . the csi map has a programmable i 2 c slave address, which is programmed using register 0xfe in the user sub map of the main map. the def ault value for the csi map address is 0x00; however, the csi map cannot be accessed until the i 2 c slave address is reset. the recommended i 2 c slave address for the csi map is 0x88. to reset the i 2 c slave address of the csi map, write to the csi_tx_slave_ address[7:1] bits in the main register map (address 0xf e [7:1]). set these bits to a value of 0x88 (i 2 c write address; i 2 c read address is 0x89). sub_usr_en bits , address 0x0e[6:5] the adv7282 / adv7282 - m m ain map contains three sub maps: the user sub map, the interrupt/vdp sub map, and user sub map 2 (see figure 16 ). the u ser s ub m ap is available by default. the other two sub maps are accessed using the sub_usr_en bits . when programming of the interrupt/ vdp map or user sub map 2 is completed, it is necessary to write to the sub_usr_en bits to return to the user sub map.
data sheet adv7282 rev. a | page 27 of 32 pcb layout recommend ations the adv7282 / adv7282 - m is a high precision, high speed, mixed - signal device. to achieve maximum performance from the part, it is important to us e a well - designed pcb. th is section provides guide lines for designing a pcb for use with the adv7282 / adv7282 - m . analog interface in puts w hen routing the analog interface inputs on the pcb , k eep t rack lengths to a minimum . use 75 ? trace impedances when possible ; trace impedances other than 75 ? increase the chance of reflections. power supply decoupl ing it is recommended that each power supply pin be decoupled with 1 00 n f and 10 nf capacitor s . the basic principle is to place a decoupling capacitor within approximately 0.5 c m of each power pin. a void placing the decoupling capacitor s on the opposite side of the pcb from the adv7282 / adv7282 - m because doing so int roduc es inducti ve vias in the path. place t he decoupling capacitors between the power plane and the power pin. current should flow from the power plane to the capacitor and then to the power pin. do n ot apply the power connection between the capacitor and the power pin. the best approach is to p lac e a via near, or be neath , the decoupling capac i - tor pads down to the power plane (see figure 17). supply ground 10nf 100nf via to supply via to gnd 1 1534-013 figure 17 . recommended power supply decoupling it is especial ly important to maintain low noise and good stability for the p vdd pin . careful attention must be paid to regulation, filtering, and decoupling. it is highly desirable to provide sep arate regulated supplies for each circuit group (a vdd , d vdd , d vddio , m vdd , and p vdd ). note that m vdd only applies to the adv7282 - m model. some graphic controllers use substantially different lev els of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). this disparity can result in a measurable change in the voltage supplied to the analog supply regulator, which can , in turn , produce changes in the regu - lated analog supply voltage. this problem can be mitigated by regulating the analog supply, or at least the p vdd supply , from a different, cleaner power source, for example, from a 12 v supply. using a single ground plane for the entire board i s also recom - mended. experience has shown that the noise performance is the same or better with a single ground plane. using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. vrefn an d vrefp pins place the circuit associated with the vrefn and vrefp pins as close as possible to the adv7282 / adv7282 - m and on the sa me side of the pcb as the part . digital outputs the adv7282 digital outputs are : intrq , llc, p0:p7. the adv72 82- m digital outputs ar e: intrq , gpo0 to gpo2. m inimize the trace length that the digital outputs must drive. longer traces have higher capacitance, requiring more current and, in turn, causing more internal digital noise. shorter t races reduce the possibility of reflections. adding a 30 ? to 50 ? series resistor can suppress reflections, reduce emi, and reduce current spikes inside the adv7282 / adv7282 - m . if series r esistors are used, place them as close as possible to the pins of the adv7282 / adv7282 - m . however, try not to add vias or extra lengt h to the output trace in an attempt to place the resistors closer. if possible, limit the capacitance that each digital output must drive to less than 15 pf. this recommendation can be easily accom - modat ed by keeping traces short and by connecting the outp uts to only one device. loading the outputs with excessive capacitance increases the current transients inside the adv7282 / adv7282 - m , creating more digital noise on the power supplies. exposed metal pad the adv7282 / adv7282 - m has an exposed metal pad on the bottom of the package. this pad must be soldered to ground . th e exposed pad is used for proper heat dissipation , noise suppression , and mechanical strength. digital inputs the digital inputs o f the adv 7282/ adv7282 - m are designed to work with 1.8 v signals (3.3 v for d vddio ) and are not tolerant of 5 v signals. extra components are required if 5 v logic signals must be applied to the decoder. mipi outputs (d0p, d0n, clkp, clk n) adv7282 - m o nly it is recommended that the mipi output traces be kept as short as possible and on the same side of the pcb as the adv7282 - m device. it is also recommended that a solid plane ( preferably a ground plane ) be placed on the layer adjacent to the mipi traces to provide a solid reference plane. mipi transmission operates in both differential an d single - ended modes . during high speed transmission, the pair of output s operates in differential mode ; i n low power mode , the pair operate s as two independ ent single - end ed traces . t here - fore, it is recommended that each output pair be routed as two loose ly coupled 50 ? single - ended traces to reduce the risk of c rosstalk between the two traces in low power mode .
adv7282 data sheet rev. a | page 28 of 32 typical circuit conn ection figure 18 provides an example of how to connect adv7282 . for detailed schematics of the adv7282 evaluation board, contact a local analog devices field applications engineer or an analog devices distributor. 11534-203 sclk 30 sclk reset 27 reset pwrdwn 31 pwrdwn sdata 29 sdata llc 32 llc intrq 26 intrq p0 12 p0 p1 11 p1 p2 10 p2 p3 9 p3 p4 8 p4 p5 7 p5 p6 6 p6 p7 5 p7 p0 to p7 28.63636mhz 47pf 47pf xtalp 14 xtaln 15 0.1f vrefp 19 vrefn 20 alsb 28 4k? dgnd 1 dgnd 4 16 2 13 3 21 0.1f 10nf 0.1f 10nf 0.1f 10nf 0.1f 10nf 0.1f 10nf adv7282 17 18 a in 1 a in 2 a in 1 a in 2 24 25 a in 3 a in 4 a in 3 a in 4 d vdd _1.8v d vddio _3.3v a vdd _1.8v d vddio _3.3v d vdd _1.8v a vdd _1.8v p vdd _1.8v ycrcb 8-bit itu-r bt.656 data d vddio alsb tied high: i 2 c address = 0x42 alsb tied low: i 2 c address = 0x40 p v d d a v d d d v d d d v d d d v d dio locate close to, and on the same side of the pcb as, the adv7282 locate vrefp and vrefn capacitor as close as possible to the adv7282 and on the same side of the pcb as the adv7282 diag1 diag2 22 diag1 23 diag2 0 . 1 f 0 . 1 f 430 150 430 1 9.1 0 . 1 f 0 . 1 f 430 75 430 a i n 1 a i n 2 diag1 a i n 3 a i n 4 diag2 fully differential cvbs input pseudo differential cvbs input k k 9.1 k 1 k 1.3k 1.3k 1.3k 1.3k diff1+ diff1? diff2+ diff2? figure 18 . typical connection diagram, adv7282
data sheet adv7282 rev. a | page 29 of 32 figure 19 provides an example of how to connect the adv7282 - m . for detailed schematics of the adv7282 - m evaluation board, contact a local analog devices field applications engineer or an analog devices distributor. s c l k 3 1 s c l k s d a t a 3 0 a i n 1 1 7 a i n 2 1 8 d i a g 1 2 2 2 3 6 7 8 9 1 0 1 1 1 2 v r e f p v r e f n 2 8 . 6 3 6 3 6 mh z 4 7 p f 4 7 p f x t a l p 1 4 x t a l n 1 5 a l s b 2 9 d v d d i o 4 k ? d g n d 1 d g n d 4 1 6 2 3 d v d d i o _ 3 . 3 v d v d d _ 1 . 8 v 2 1 a v d d _ 1 . 8 v m v d d _ 1 . 8 v p v d d _ 1 . 8 v 0 . 1 f 1 0 n f 0 . 1 f 1 0 n f 0 . 1 f 1 0 n f 0 . 1 f 1 0 n f r e s e t r e s e t a i n 3 p w r d w n p w r d w n 3 2 2 8 0 . 1 f 1 0 n f 1 3 0 . 1 f 1 9 2 0 2 4 2 5 2 6 2 7 d 0 p d 0 n c l k p c l k n a i n 4 a i n 5 a i n 6 g p o 2 g p o 1 g p o 0 g p o 2 g p o 1 g p o 0 d 0 p d 0 n c l k p c l k n 5 i n t r q i n t r q a i n 5 a i n 6 d i a g 2 0 . 1 f 0 . 1 f 430 150 430 1 9.1 0 . 1 f 0 . 1 f 430 75 430 a i n 1 a i n 2 diag1 a i n 3 a i n 4 diag2 5 1 24 0 . 1 f a i n 5 s i n g l e - e n d e d 5 1 24 0 . 1 f a i n 6 a i n 1 a i n 2 a i n 3 a i n 4 diag1 diag2 fully differential cvbs input pseudo differential cvbs input k k 9.1 k 1 k cvbs input example s i n g l e - e n d e d cvbs input example d vddio _3.3v m vdd _1.8v a vdd _1.8v d vdd _1.8v adv7282-m locate vrefn and vrefp capacitor as close as possible to the adv7282-m and on the same side of the pcb as the adv7282-m 11534-014 p vdd m vdd a vdd d vdd d vddio 1.3k 1.3k 1.3k 1.3k alsb tied high: i 2 c address = 0x42 alsb tied low: i 2 c address = 0x40 locate close to, and on the same side of the pcb as,the adv7282-m sdata diff1+ diff1? diff2+ diff2? f igure 19 . typical connection diagram
adv7282 data sheet rev. a | page 30 of 32 outline dimensions 08-16-2010-b 1 0.50 bsc bottom view top view pin 1 indi c ator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r seating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min * 3.75 3.60 sq 3.55 * compliant to jedec standards mo-220-whhd-5 with the exception of the exposed pad dimension. figure 20. 32-lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp-32-12) dimensions shown in millimeters ordering guide model 1, 2 temperature range package description package option ADV7282WBCPZ ?40c to +105c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-12 ADV7282WBCPZ-rl ?40c to +105c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-12 ADV7282WBCPZ-m ?40c to +105c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-12 ADV7282WBCPZ-m-rl ?40c to +105c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-12 eval-adv7282mebz evaluation board for the adv7282-m 1 z = rohs compliant part. 2 w = qualified for auto motive applications. automotive products the adv7282w models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specific ations that differ from the commercial models; therefore, desi gners should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models.
data sheet adv7282 rev. a | page 31 of 32 notes
adv7282 data sheet rev. a | page 32 of 32 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors) . ? 2013 analog devices, inc. all rights reserved. trademarks and registe red trademarks are the property of their respective owners. d11534 - 0 - 11/13(a)

▲Up To Search▲

Price & Availability of ADV7282WBCPZ

	To Download ADV7282WBCPZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .